1. Technical Field
Various embodiments relate generally to a semiconductor apparatus, and more particularly, to a semiconductor apparatus with a test circuit.
2. Related Art
When a semiconductor apparatus is fabricated, a test process is performed to determine whether the semiconductor apparatus normally operates. This is done by checking whether or not normal data is outputted after an electrical signal has been applied to a pad of the semiconductor apparatus.
Recently, a semiconductor apparatus in which semiconductor chips are stacked and coupled with through silicon vias (TSVs) has been developed. Such a semiconductor apparatus may employ a bump pad structure for an input/output pad. That is, the plurality of chips is coupled through TSVs inside a semiconductor package, and the bump pad serves to transmit signals between the TSVs of the respective chips. Since the bump pad handles a small data output load, an output driver to output data to the bump pad has restrained drivability compared to a general semiconductor apparatus.
Thus, the semiconductor apparatus cannot handle the load of a probe test device using only the bump pad structure. Accordingly, the semiconductor apparatus includes a separate circuit and pad for the probe test.
FIG. 1 is a block diagram of a semiconductor apparatus with a general bump pad structure.
The semiconductor apparatus of FIG. 1 includes a data output unit 1, an input/output pad 2, a test output unit 4, and a probe pad 5.
During a read operation, data stored in a memory cell (not illustrated) is transmitted through a data line GIO. The data output unit 1 is configured to receive the transmitted data DATA and transmit output data DO to the input/output pad 2. The input/output pad 2 may have a small data output load and may be formed as a bump pad.
The probe pad 5 is separately provided to perform a probe test for the semiconductor apparatus. The test output unit 4 receives the transmitted data DATA and outputs test output data TDO, when a test mode signal TM (not shown) is activated. The data drivability of the test output unit 4 is set to be larger than that of the data output unit 1. The test output data TDO may be outputted through the probe pad 5.
The probe test for the semiconductor apparatus may be performed using the test output unit 4 and the probe pad 5. Through the probe test, data stored in the semiconductor apparatus may be outputted and probed to verify whether memory cells have a defect or not.
However, latent defects of the semiconductor apparatus not only may exist in memory cells, but also may exist in various parts of the semiconductor apparatus. For example, the latent defects may exist in a data output path for outputting data externally, such as to an output driver and related circuits. Therefore, there is a demand for a method to screen the latent defects during the probe test to increase the operation and reliability of the semiconductor apparatus.